Layout Engineer, DEG Layout
Core
Design and development of critical analog, mixed-signal, custom digital blocks, and full chip level integration for advanced memory and semiconductor technologies.
Role type
Senior IC Layout Design Engineer (Analog/Mixed-Signal)
Builds
Analog and mixed-signal IPs for DRAM chips used in AI, high-performance computing, and High Bandwidth Memory.
Domain
Semiconductor / VLSI / Memory Technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/custom layout design in advanced CMOS processes, Cadence VLE/VXL, Mentor Calibre DRC/LVS, layout of critical blocks (PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier), Analog Layout fundamentals (Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitics), design hierarchy and architecture understanding for Memory designs, physical verification of custom layout
Preferred skills
Multiple tape-out support experience, proactive exploration of AI-related tools
Technologies
Cadence VLE, Cadence VXL, Mentor Calibre
Responsibilities
Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support; Perform layout verification like LVS/DRC/Antenna, quality check and support documentation; Responsible for on-time delivery of block-level layouts with acceptable quality; Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule milestones; Contribute to effective project-management; Effectively communicating with Global engineering teams to assure the success of layout project
Seniority
Mid-Senior, hands-on IC
