Senior Engineer IP Verification - Digital Design Verification
Core
Define verification scope and strategy for block/chip RTL verification of DRAM architectures, developing testbenches and vectors to ensure functional readiness for tapeout.
Role type
Senior IC digital design verification engineer (DRAM)
Builds
DRAM memory blocks and chips
Domain
Semiconductor / Memory / Digital Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL verification, SV-UVM, directed and constrained-random testing, functional coverage analysis, RTL debugging, Perl scripting, Python scripting
Preferred skills
AI tool adoption for verification workflows, cross-functional collaboration on new verification flows
Technologies
Virtuoso, Xcellium, Simvision, Verdi/Verisium
Responsibilities
Define verification scope and strategy for block/chip RTL; Develop and maintain SV-UVM testbenches and test vectors; Run regressions and analyze failure triage; Close verification metrics (functional/code coverage) to demonstrate tapeout readiness; Debug RTL/testbench issues and partner with design engineers to identify root causes; Provide verification status summaries to stakeholders
Seniority
Senior, hands-on IC
