AIML enhanced Design/Verification Methodology Engineer
Core
Develop and execute verification strategies for complex digital designs using AIML-enhanced methodologies, including generative-AI agents and automated RTL generation.
Role type
Senior IC Design/Verification Methodology Engineer (ASIC/SoC)
Builds
UVM-based testbench environments, verification plans, and silicon-quality digital designs from RTL to tapeout.
Domain
Semiconductor hardware design and verification (ASIC/SoC)
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, digital design fundamentals (RTL, timing, synthesis), root cause analysis, coverage-driven verification, AIML concepts and agentic workflows, industry simulation tools (Synopsys VCS, Cadence Xcelium, Mentor Questa)
Preferred skills
Formal verification, emulation/FPGA prototyping, Python/TCL scripting, power-aware verification (UPF/CPF), high-speed serial interface verification
Technologies
SystemVerilog, UVM, Python, TCL, Synopsys VCS, Cadence Xcelium, Mentor Questa, JasperGold, VC Formal, Palladium, Protium, Veloce
Responsibilities
Architect and maintain UVM-based testbench environments; create verification plans with coverage goals; automate RTL generation from specifications; perform root cause analysis of failures; evaluate industry verification tools.
Seniority
Mid-Senior, hands-on IC
