HBM IO Architecture, Principal Engineer
Core
Technical authority for HBM IO circuits and PHY architecture, leading multi-generation initiatives in TSV link definition, IO training, and silicon validation to enable high-bandwidth, low-power AI and HPC platforms.
Role type
Principal Engineer, Heterogeneous Integration (HBM IO Design Architecture)
Builds
Industry-leading HBM solutions for AI, ML, and high-performance computing platforms
Domain
Semiconductor / Memory / High-Speed IO / TSV
Deliverable
production ML models
Required skills
Analog and mixed-signal CMOS circuit design, high-speed IO architecture (Rx/Tx, PLL, DLL, DCC, phase interpolators, equalizers), TSV link definition, IO training features, silicon validation, system-level thinking
Preferred skills
HBM, DRAM, or advanced memory interface design, patents/publications in high-speed IO or TSV, experience with UCIe or JEDEC memory standards, technical leadership across multi-disciplinary programs
Technologies
TSV, HBM, LPDDR, UCIe, JEDEC standards
Responsibilities
Define and own HBM IO and data path architecture across product generations, Architect and analyze TSV-based HBM link schemes, Define and drive HBM PHY IO training features, Architect high-speed IO circuits for the HBM interface die, Establish IO and TSV design standards and drive alignment across teams
Seniority
Principal, technical authority & long-term architectural direction
