Principal Mixed Signal Engineer, Texas Institute for Electronics
Core
Develop next-generation digital subsystems and compute fabrics for 2.5D/3D microsystems, enabling scalable, high-bandwidth integration across AI, HPC, and wireless acceleration platforms.
Role type
Principal Mixed Signal Engineer (high-speed I/O & SerDes)
Builds
High-speed mixed-signal I/O circuits, SerDes, clock/data recovery (CDR), equalization, and transceiver circuits for die-to-die and chip-to-chip links.
Domain
Semiconductor manufacturing, 3D heterogeneous integration, chiplet-based architectures, AI, HPC, defense electronics.
Deliverable
production ML models | product features | infrastructure
Required skills
High-speed transceiver design (TX/RX front-ends, CDR, equalization, PLLs/DLLs), Signal integrity analysis, Silicon bring-up and lab characterization, ATE test development, Analog/mixed-signal EDA tool proficiency, Cross-disciplinary collaboration, IP roadmap translation.
Preferred skills
UCIe 2.5D/3.0D physical-layer implementation, Heterogeneous integration modeling, High-speed SerDes design (>28 Gbps), Interconnect standards knowledge (UCIe, CXL, PCIe, NVLink), Publications or patents in mixed-signal design.
Technologies
Cadence Virtuoso/Spectre, Synopsys HSPICE, Ansys HFSS/SIwave, High-speed oscilloscopes, BER testers, Network analyzers.
Responsibilities
Design high-speed mixed-signal I/O circuits for UCIe interfaces; Architect and optimize SerDes and transceiver circuits; Collaborate with packaging and EDA teams to co-optimize performance; Lead silicon bring-up, bench characterization, and production testing; Engage with industry partners to influence specification development; Mentor internal design teams on mixed-signal methodologies.
Seniority
Principal, hands-on IC with mentorship responsibilities
