Senior Principal Engineer Analog Design (HBM PHY)
Core
Design and delivery of next-generation HBM PHY analog and mixed-signal solutions for AI, HPC, and hyperscale systems.
Role type
Senior Principal Analog IC Design Engineer (HBM PHY)
Builds
High-speed interface IP for data infrastructure (AI, HPC, hyperscale)
Domain
Semiconductor / High-speed Analog IC Design
Deliverable
production ML models | product features
Required skills
Analog/mixed-signal IC design, high-speed interface design (multi-Gbps), TX/RX circuit design, clocking (DLL/PLL), equalization, signal integrity (SI), power integrity (PI), silicon bring-up and debug, system-level modeling, cross-functional architecture leadership
Preferred skills
HBM PHY or memory interface design (HBM3/HBM4), SerDes/DDR/LPDDR/GDDR PHY design, advanced packaging (2.5D/3D, chiplets, interposers), CDR design
Technologies
HBM4, HBM3, SerDes, DDR, LPDDR, GDDR, 2.5D/3D packaging, interposers
Responsibilities
Own analog/mixed-signal architecture of HBM PHY (TX/RX, clocking, DLL/PLL, reference circuits); Lead design of critical high-speed blocks (IO drivers, receivers, equalization, clock distribution); Define and drive SI, PI, and jitter/noise budgets; Partner with logic/RTL architects on training flows and calibration algorithms; Drive HBM4 implementation to silicon; Lead design reviews, modeling, and simulation methodologies; Drive post-silicon bring-up, characterization, and debug; Engage with memory vendors for interface compliance
Seniority
Principal, hands-on IC design with technical leadership