Sr/Staff Design Verification Engineer, HBM Verification Architecture
Core
Developing verification plans and architecture for next-generation High Bandwidth Memory (HBM) DRAM products used in AI and ML applications.
Role type
Senior IC design verification engineer (HBM architecture)
Builds
Modular, scalable verification solutions for 2.5D & 3D package integration HBM designs
Domain
Semiconductor / Memory / AI & ML infrastructure
Deliverable
production ML models
Required skills
Verilog, FastSpice, mixed-signal verification, co-simulation, real number modeling, schematic-based verification, RTL design verification, testbench architecture, SoC verification, IP-level verification, debug of pre-silicon and post-silicon issues, JEDEC specifications
Preferred skills
Patents or publications in verification solutions, building or improving verification flows, memory product experience
Technologies
TSV, RTL2GDS, GenAI applications
Responsibilities
Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification; Support co-verification of the overall system and participate in customer interactions; Build and improve verification methodology components and GenAI applications; Evaluate and debug pre-silicon and post-silicon issues
Seniority
Senior, hands-on IC