Manager, Advanced Packaging Design Enablement Engineering (APDEE)
Core
Lead die design and layout engineering for High Bandwidth Memory (HBM) packaging, defining strategy from concept to tape-out to enable world-class product integration.
Role type
Senior IC Manager, Advanced Packaging Die Design & Layout
Builds
Next-generation HBM products for AI, HPC, and data center applications
Domain
Semiconductor manufacturing, Advanced Packaging, Memory Technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical design and layout, TSV design, Micro-bump layout, Backside RDL, DRC/LVS/ERC sign-off flows, Foundry PDK rule interpretation, Power integrity, Signal integrity, Thermal considerations, Parasitic extraction, EDA tools (Cadence Virtuoso, Innovus, Mentor Calibre, Synopsys IC Compiler)
Preferred skills
Hybrid bonding, Direct bond interconnect (DBI), Chiplet architecture, Layout automation scripting (Skill, Python, Tcl), Reliability physics (electromigration, stress voiding)
Technologies
Cadence Virtuoso, Innovus, Mentor Calibre, Synopsys IC Compiler, TSV, Micro-bump, RDL, PWF, DFT
Responsibilities
Lead and mentor a team of die build and layout engineers; Define die floorplanning strategy including TSV grid placement and micro-bump array layout; Establish and maintain die design rules aligned with foundry PDK requirements; Perform electrical simulations to understand fail mode mechanisms; Engage with integration teams on BEOL design and advanced packaging requirements.
Seniority
Senior, hands-on IC with management responsibilities