Senior Staff PCB Layout Design Engineer
Core
Lead architect of physical medium connecting breakthrough AI silicon to the world, owning layout of high-complexity, high-layer-count PCBAs ensuring pristine 112G/224G SerDes signals and high-power delivery.
Role type
Senior Staff PCB Layout Design Engineer (Hardware Systems Architect)
Builds
High-complexity AI accelerator cards (PCIe form factors) and massive system baseboards for Digital In-Memory Computing platforms
Domain
AI Hardware / High-Speed PCB Design / Server Infrastructure
Deliverable
production ML models
Required skills
High-speed routing (112G/224G SerDes, PCIe Gen5/6, CXL, DDR5/HBM), Cadence Allegro Constraint Manager mastery, SKILL/Python/TCL automation, HDI/ELIC design, Power Delivery Network (PDN) strategy, Stack-up and material science (Megtron 7/8), DFM/DFT/DFA management
Preferred skills
Library Management System establishment, PLM/PDM integration, PCB warpage mitigation for large-form-factor ASICs and MCMs
Technologies
Cadence Allegro, SKILL, Python, TCL, Megtron 7/8
Responsibilities
Lead full-cycle system layout for AI accelerator cards and baseboards; Architect and manage Constraint Manager hierarchy for high-speed routing rules; Develop automation scripts for layout tasks and DRC checks; Execute layout for ultra-high-speed interfaces and custom die-to-die interconnects; Optimize power delivery with complex PDN strategies; Define PCB stack-ups and select advanced low-loss materials; Interface with fabricators to ensure DFM/DFT/DFA requirements are met
Seniority
Senior Staff, hands-on IC with strategic process ownership