Engineer, DPG LPDDR Verification
Core
Senior verification engineer driving end-to-end verification of high-speed DDR/LPDDR memory products using gate-level simulation and UVM methodologies.
Role type
Senior IC verification engineer (memory/DRAM)
Builds
High-speed DDR4, LPDDR4, DDR5, and LPDDR5 memory chips operating up to 6400MT/s
Domain
Semiconductor memory (DRAM/SRAM) and low-power power management
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, gate-level simulation, SPICE, DRAM architecture knowledge, AMS verification, co-simulation, test bench development, regression analysis
Preferred skills
AI-based automation tools, experience with emerging memory architectures
Technologies
SystemVerilog, UVM, SPICE, Verilog, simulation tools
Responsibilities
Guide verification effort direction and methodology; develop test cases and stimulus for functional coverage; simulate, analyze, and debug pre-silicon full chip designs; maintain test benches and run regressions; collaborate globally on new verification flows
Seniority
Senior, hands-on IC
