Principal Engineer- DEG Layout
Core
Design and develop analog, mixed-signal, custom digital block, standard cell, and full chip layouts for memory and storage solutions.
Role type
Principal IC Layout Engineer
Builds
Custom digital blocks, standard cells, and full chip layouts for DRAM, NAND, and NOR memory products
Domain
Semiconductor manufacturing (Memory/Storage)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout, mixed-signal layout, custom digital block layout, standard cell design, full chip layout, LVS verification, DRC verification, Antenna rule checking, Shield design, Matching verification, Latch-up analysis, EM/IR/Totem checks, Auto placement, Auto routing, Skill coding, Automation, AI integration for layout optimization
Preferred skills
Leadership in planning and scheduling, Team mentoring, Cross-functional communication with global engineering teams
Technologies
Auto placement tools, Auto routing tools, LVS/DRC verification tools, AI tools for layout reduction
Responsibilities
Perform layout verification including LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, and quality documentation; Develop digital block layouts using auto placement and route tools; Guide team members in sub-block-level layout execution and review their work; Reduce layout effort by implementing AI solutions; Demonstrate leadership in planning, area/time estimation, scheduling, and delegation to meet project schedules.
Seniority
Principal, hands-on IC with leadership responsibilities
