Principal Engineer- DEG Layout
Core
Lead layout design and development for critical analog, mixed-signal, custom digital blocks, standard cells, and full chip levels in memory and storage solutions.
Role type
Principal IC Layout Engineer
Builds
Custom digital blocks, standard cells, and full chip layouts for DRAM, NAND, and NOR memory products
Domain
Semiconductor / Memory and Storage
Required skills
Analog layout, Mixed-signal layout, Custom digital block layout, Standard cell design, Full chip layout, LVS verification, DRC verification, Antenna rule checking, Shielding design, Matching design, Latch-up analysis, EM/IR/Totem checks, Auto placement, Auto routing, Skill coding, Automation, AI for layout optimization, Project planning, Team leadership, Technical communication
Preferred skills
AI tool integration for layout reduction, Cross-functional collaboration with global teams
Technologies
Auto placement tools, Auto routing tools, LVS/DRC checkers, Skill coding environments
Responsibilities
Perform layout verification including LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, and quality documentation; Develop digital block layouts using auto placement and route tools; Guide team members in sub-block-level layout execution and review work; Reduce layout effort by implementing AI solutions; Demonstrate leadership in planning, scheduling, and delegation to meet project schedules; Communicate effectively with global engineering teams to ensure project success.
