Senior/Staff Engineer - HIG HBM - PE Design Validation
Core
Validating Heterogeneous Integration Group (HBM) designs through simulation, data analysis, and ATE/bench analysis to ensure performance and reliability for ML/AI applications.
Role type
Senior/Staff PE Design Validation Engineer
Builds
High Bandwidth Memory (HBM) packages with stacked DRAM and logic chips for AI/ML workloads
Domain
Semiconductor manufacturing, VLSI, and High Bandwidth Memory (HBM)
Deliverable
production ML models | product features
Required skills
VLSI design, semiconductor process knowledge, device physics, Verilog/VHDL/System Verilog, schematic and layout knowledge, statistical data analysis, hardware/software debugging
Preferred skills
JEDEC specification expertise, AI-enabled enhancement identification
Technologies
ATE, simulation tools, statistical analysis tools
Responsibilities
Interface between Design, Manufacturing, Test, and Quality departments; Perform validation work on test modes and designs; Resolve manufacturing and test issues via debugging and simulation; Analyze engineering data for risk assessment; Create internal architecture documentation based on JEDEC specs
Seniority
Senior/Staff, hands-on IC