Staff/Principal Engineer - HBM Design for Test (DFT)
Core
Define, deploy, and sustain best-in-class Design for Test (DFT) solutions for High Bandwidth Memory (HBM) core and base dies, focusing on logic die MBIST support and architectural definitions.
Role type
Staff/Principal Engineer - HBM Design for Test (DFT)
Builds
HBM memory products with robust, scalable, and manufacturable DFT architectures
Domain
Semiconductor / Memory / HBM
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture definition, MBIST fundamentals, logic test concepts, HBM/DRAM memory architecture knowledge, RTL debug, Verilog, analog simulation, timing closure, floorplanning, congestion/power/area tradeoff analysis
Preferred skills
IEEE 1500 / DFT access mechanisms, broadcast test concepts, first silicon/qualification/high-volume manufacturing debug experience
Technologies
Verilog, analog simulation tools
Responsibilities
Define and implement logic die MBIST architectures including controller interaction and sequencing; Own test definitions and DFT entry flows for MBIST, logic test, and interface test; Partner with SoC architects to ensure scalable DFT integration; Support RTL debug and functional verification for DFT features; Provide guidance on DFT-friendly floorplanning and implementation practices; Mentor junior engineers and support technical skill development
Seniority
Staff/Principal, hands-on IC with architectural definition and mentorship
