NAND PI Design Rule Snr Engineer
Core
Define physical design rules for Non-Volatile Memory (NVM) technologies from conception to production, ensuring accuracy for layout and mask generation.
Role type
Senior IC Physical Design Rule Engineer (NVM)
Builds
Physical design rules, mask data generation algorithms, and layout verification data for NAND/NVM products.
Domain
Semiconductor manufacturing / Non-Volatile Memory (NAND, NVM)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical design rule definition, process integration knowledge, layout and architecture feasibility evaluation, DRC support, mask data generation algorithms, multi-disciplinary collaboration
Preferred skills
Experience with NVM technology ramp, interaction with physical verification teams
Technologies
DRC tools, mask data generation systems, layout and mask generation workflows
Responsibilities
Define physical design rules for current and future NVM technologies, interact with process integration teams to maintain accurate design rules, evaluate layout and architecture feasibility with design teams, support DRC of base and mask layers, define algorithms for mask data generation, collaborate on layout and mask generation issues
Seniority
Senior, hands-on IC
