Principal Engineer - STA/Synthesis
Core
Designing and analyzing digital and analog circuits for memory products, focusing on static timing analysis (STA) and timing closure for core die.
Role type
Staff IC verification engineer (STA/Synthesis)
Builds
High-performance DRAM, NAND, and NOR memory and storage products
Domain
Semiconductor manufacturing / Memory technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static timing analysis (block, top-level, cell), constraint writing, circuit understanding (block to full chip), parasitic modeling, verification simulation, STD cell characterization, ARC writing (primeLib, Silicon smart)
Preferred skills
AI tool usage, cross-group collaboration, innovation in memory generations
Technologies
primeLib, Silicon smart, industry standard simulators
Responsibilities
Perform static timing analysis on DRAM blocks, top levels, and cells; write constraints and analyze STA reports; report violations and own timing closure; assist in design validation, reticle experiments, and tape-out revisions; characterize STD cells and write ARC; collaborate with design and verification teams globally.
Seniority
Staff, hands-on IC
