Staff Design Verification Engineer, DRAM
Core
Develop and verify high-density DRAM and emerging memory products (up to 32Gb) using mixed-signal verification methodologies.
Role type
Staff Design Verification Engineer (DRAM)
Builds
Next-generation DDR/LPDDR memory chips with advanced low-power and power management technologies.
Domain
Semiconductor / Memory / DRAM
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Mixed signal verification, SystemVerilog/UVM, HSPICE/FINESIM, Python/Perl scripting, SVA, LLMs and Agentic AI tools, debugging, circuit design understanding
Preferred skills
Master's degree in Electrical/Computer Engineering, 3+ years experience, cross-functional collaboration in semiconductor environment, memory product development workflows
Technologies
HSPICE, VerilogHDL, FINESIM, SystemVerilog, UVM, Python, Perl
Responsibilities
Develop patterns and regressions to increase function coverage for DRAM architectures, debug failures and lead bug tracking, co-work on developing new verification tools and flows, own and lead design projects and mentor junior engineers, create verification plans from functionality specifications, develop and maintain test benches and test vectors
Seniority
Staff, hands-on IC with mentorship
