ASIC / FPGA Design Verification Engineer - (Associate or Experienced)
Core
Develop adaptable verification engineers who build strong technical fundamentals and become independent owners of assigned verification scope for ASIC, FPGA, and SoC verification activities.
Role type
ASIC/FPGA/SoC Design Verification Engineer (Associate or Experienced)
Builds
Digital subsystems for advanced aerospace programs including space systems, satellite technologies, NASA mission support, aviation platforms, and communications systems.
Domain
Aerospace / Digital Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, simulation concepts, debug methods, coverage approaches, requirements traceability, digital verification methodology
Preferred skills
UVM, OOP, coverage-driven verification, requirements traceability, reusable UVC development, system-level debug
Technologies
SystemVerilog, UVM
Responsibilities
Execute assigned verification tasks and progressively increase ownership; Develop simulation, debug, coverage, and requirements traceability skills; Contribute to SystemVerilog and UVM environments, tests, UVCs, and reusable infrastructure; Support integration investigations and system-level debug activities; Contribute to verification objectives, coverage assessments, and closure activities; Own verification scope of moderate complexity at Level III.
Seniority
Associate (Level 2) or Experienced (Level 3)
