Static Timing Analysis (STA) Engineer
Core
Ensuring timing convergence for state-of-the-art digital ICs/SoCs and FPGAs across Boeing's Defense and Security enterprise, from early design stages to flight insertion.
Role type
Senior IC Static Timing Analysis (STA) Engineer
Builds
High-integrity, low SWAP-C flight computers and complex SoCs using ARM IP
Domain
Aerospace defense electronics, ASIC/FPGA physical design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
STA analysis and convergence, timing constraint generation (setup/hold/RAT/skew), RTL to GDS flow, Synopsys Primetime, Synopsys Design Compiler, Python/TCL/Perl/Unix scripting, cross-domain timing path closure
Preferred skills
Leading static timing closure, training new hires, space-based design techniques, radiation mitigation, DFT implications, multiple static timing tools (Cadence Tempus, Vivado), Synopsys Fusion Compiler, Formality
Technologies
Synopsys Primetime, Synopsys Design Compiler, Cadence Tempus, Vivado, Synopsys Fusion Compiler, Cadence Formality
Responsibilities
Perform pre-layout and post-layout timing analysis, generate tool-independent timing constraints, collaborate with IP teams and EDA vendors for design closure, train new engineers
Seniority
Senior, hands-on IC
