ASIC Floorplan Design Engineer - New College Grad 2026
Core
Design and optimize floorplans for next-generation GPUs and SoCs, influencing early design decisions to solve timing and routing congestion.
Role type
ASIC Floorplan Design Engineer (New College Grad)
Builds
High-performance GPUs and System-on-Chips (SoCs) for AI, autonomous driving, and consumer graphics.
Domain
Semiconductor / VLSI / Hardware Engineering
Deliverable
production ML models | product features
Required skills
VLSI design, Computer Architecture, Verilog/System Verilog, Physical Design methodologies, Chip floorplanning, Power/Clock distribution, Python, Perl, C/C++
Preferred skills
Large-scale ASIC floorplan development
Technologies
Verilog, System Verilog, Python, Perl, C/C++
Responsibilities
Develop and optimize floorplans during early chip development; Drive area review process; Solve timing and routing congestion issues; Build tools to optimize chip area and execution speed.
Seniority
Entry-level (New College Grad)
