ASIC Engineering Intern, Networking Chip Design - 2027
Core
Intern role focused on implementing next-generation Switch Silicon chips for high-speed communication devices, optimizing throughput and latency.
Role type
ASIC Engineering Intern (Networking Chip Design)
Builds
High-speed communication devices (Switch Silicon chips)
Domain
Semiconductor / Networking
Deliverable
production ML models | product features
Required skills
RTL design, RTL verification, scripting (Python/Perl), full-chip workflow understanding, test facility development
Preferred skills
Experience in RTL design or verification, strong scripting skills
Technologies
Python, Perl
Responsibilities
Understand full-chip working flow and build infrastructure for automation and efficiency; work in combined design and verification teams to develop test facilities for quality assurance; collaborate with Architecture, Micro-Architecture, and Firmware teams.
