ASIC Engineer
Core
Develop and deploy innovative RTL design-quality methodologies (CDC, RDC, lint, structural checks) to improve RTL quality, project predictability, and silicon readiness.
Role type
Senior IC ASIC Engineer (RTL Design Methodology)
Builds
Digital implementation and microarchitecture flows for NVIDIA CPU programs
Domain
Semiconductor / ASIC Design / RTL Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (RTL quality flows)
Required skills
Verilog/SystemVerilog, CDC/RDC analysis, digital design/microarchitecture, Python/Tcl/Perl scripting, root-cause analysis, Linux development environments, timing constraints, low-power verification
Preferred skills
RTL integration/debugging, Meridian/SpyGlass/VC CDC tools, UPF implementation, static timing analysis, formal verification
Technologies
Verilog, SystemVerilog, Python, Tcl, Perl, Shell, Linux, Meridian, SpyGlass, VC CDC, Questa CDC, Design Auditor
Responsibilities
Analyze flow results to identify root causes across RTL, constraints, and tools; Establish quality requirements and monitor regressions; Collaborate across RTL, DFT, and physical-design teams to resolve issues; Assess and integrate new tool releases; Improve automation and reporting through scripting.
Seniority
Senior, hands-on IC
