Power Validation Engineer
Core
Own end-to-end power characterization of ASICs and mezzanine card platforms from silicon bring-up through production qualification.
Role type
Senior IC power validation engineer (ASIC/system-level)
Builds
ASICs, mezzanine cards, and system-level power distribution networks for frontier AI inference workloads
Domain
Semiconductor hardware / AI infrastructure / Power electronics
Deliverable
production ML models | product features | infrastructure
Required skills
ASIC power delivery validation, PDN impedance analysis, VRM topology expertise, precision measurement instrumentation, power transient profiling, automated test framework development, root cause failure analysis, silicon bring-up experience
Preferred skills
High-voltage testing, AI accelerator power characterization, BMC firmware integration, Python for test automation
Technologies
VNA, oscilloscopes, precision shunts, isolated differential probes, PMBus, OpenBMC, IPMI, Linux kernel power management
Responsibilities
Design and execute power measurement campaigns across voltage rails under realistic LLM inference workloads; validate PDN performance and translate findings to PCB/package design; profile power transients and correlate with on-die performance data; run extended stress workloads to surface reliability risks; validate power sequencing and telemetry accuracy; feed characterization data to RTL and physical design teams for DVFS and leakage optimization; lead system-level power distribution network qualification; support debug and failure analysis for released products; develop automated test procedures for DUTs.
Seniority
Senior, hands-on IC
