Senior DFT Methodology Engineer
Core
Architect and develop test methodologies to make next-generation silicon testable, debuggable, and secure from the first bring-up.
Role type
Senior DFT Methodology Engineer (IC)
Builds
Test access mechanisms, memory BIST, memory dump, and DFX security methodologies for complex semiconductor chips.
Domain
Semiconductor / SoC Design / DFT
Deliverable
production ML models | product features
Required skills
SoC architecture, RTL design, verification, DFT experience, timing analysis, physical design, power analysis, silicon debug, ATE bring-up, pattern generation, cross-functional trade-offs
Preferred skills
DFT security, hardware system security, Perl/Python/Tcl scripting, mentoring, methodology adoption
Technologies
I1149.1, I1500, I1687, I1838, ATE, vendor verification tools
Responsibilities
Implement state-of-the-art designs in test access mechanisms and security methodologies; partner with timing, physical design, software, and production teams to balance cost and quality; mentor junior engineers on test designs and trade-offs.
Seniority
Senior, hands-on IC
