Senior ASIC Design Engineer - DFX
Core
Design-for-Test (DFX) architecture, design, implementation, and verification for next-generation System-on-Chip (SoC) products, spanning pre-silicon to post-silicon validation.
Role type
Senior ASIC Design Engineer (DFX)
Builds
DFT IPs (e.g., fuse controllers) and test methodologies for complex semiconductor chips
Domain
Semiconductor / SoC Design / Digital Logic
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC architecture, RTL design, DFT design and methodology, post-silicon bring-up, scripting (Python/Perl/Tcl), micro-architecture
Preferred skills
UVM, clocking, STA, place & route, power optimization
Technologies
Verilog, UVM, Python, Perl, Tcl
Responsibilities
Own architecture and design of fuse controller and other DFT IPs; Develop and enhance DFT methodologies; Define feature sets with architects and platform teams; Partner with design, verification, synthesis, timing, and backend teams; Create and execute test plans for full-chip verification; Support post-silicon bring-up, debug, and issue resolution; Mentor junior engineers on test design strategies.
Seniority
Senior, hands-on IC
