Verification Engineer - Networking IPs
Core
Develop verification components and APIs for unit and cluster level testbenches to verify queuing and scheduling algorithms and designs for datacenter chips.
Role type
Senior IC verification engineer (networking IPs)
Builds
Unit and cluster level verification environments for high-performance queuing and scheduling sub-systems
Domain
Semiconductor / Networking / Datacenter chips
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Specman, SystemVerilog, UVM, Datapath verification, Switching verification, Bus functional modeling, Functional coverage, Debugging, Analytical skills
Preferred skills
AI tools for code development, Formal verification, Automation
Technologies
Specman, SystemVerilog, UVM, FPGA
Responsibilities
Architect testbenches and craft verification environments using Specman; Define test plans, tests, and verification infrastructure; Build efficient and reusable bus functional models, monitors, checkers, and scoreboards; Implement functional coverage and own unit/cluster level verification closure; Collaborate with architects, designers, FPGA, and post-silicon teams
Seniority
Senior, hands-on IC
