Senior ASIC Floorplan Design Engineer
Core
Design and implement world-leading SOCs, CPUs, and GPUs, optimizing cost, area, performance, and power from early architecture through physical design phases.
Role type
Senior IC ASIC Floorplan Design Engineer
Builds
Next-generation GPU and SoC platforms for consumer graphics, autonomous driving, and AI.
Domain
Semiconductor / Hardware Design / AI Infrastructure
Deliverable
production ML models
Required skills
ASIC floorplan development, physical design methodologies, power/clock/reset distribution, DFT, place and route, timing closure, packaging, Python, Perl, C++, AI workflow development, multi-disciplinary collaboration
Preferred skills
Chiplet-based SOC/CPU floorplan development, large-scale ASIC floorplan experience, algorithm development
Technologies
Python, Perl, C++, DFT tools, Place and Route tools, Timing closure tools
Responsibilities
Partner with product managers, chip architects, and physical design teams to craft chip floorplans; Drive floorplan development to solve area, interconnect, and timing issues; Develop AI workflows and productivity tools for chip optimization; Identify technical risks and drive mitigation strategies.
Seniority
Senior, hands-on IC
