Senior Mixed Signal Design Engineer
Core
Architect and implement high-speed Serdes architectures reaching 80Gbps and beyond using deep-submicron CMOS and FinFET technology.
Role type
Senior IC mixed-signal design engineer (Serdes/Analog)
Builds
High-performance silicon for computer graphics, PC gaming, and accelerated computing
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features
Required skills
Analog build experience, FinFET technology, deep-submicron CMOS, Cadence Virtuoso, Spectre, HSpice, FineSim, XA, noise analysis, Monte Carlo simulations, loop stability, high-speed data path design, analog/digital circuit modeling
Preferred skills
Post-silicon bring-up and debugging, strategic floorplanning, high-speed routing mentorship
Technologies
Cadence Virtuoso, Spectre, HSpice, FineSim, XA
Responsibilities
Architect high-speed Serdes architectures and transistor-level builds; drive the entire design lifecycle from concept to silicon characterization; optimize complex circuits for peak system performance; partner with layout engineers for floorplanning and routing; lead post-silicon bring-up and debugging efforts
Seniority
Senior, hands-on IC
