Senior AI STA Engineer, Sub-chip
Core
Senior AI Static Timing Analysis (STA) Engineer performing advanced STA for complex chiplet and full chip levels, utilizing AI for timing optimization and data analysis in STA and PnR.
Role type
Senior IC physical design engineer (STA)
Builds
High-speed communication chips (Networking Silicon)
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features
Required skills
Static Timing Analysis (STA), Prime Time, signoff methodologies, timing path debugging, SDC generation, timing ecosystem generation, convergence risk identification, pre-layout to signoff quality approval
Preferred skills
AI tools orientation, Agentic Frameworks, AI prompting, Linux environments, TCL, Python, shell scripting, data collection and analysis
Technologies
Prime Time, Linux, TCL, Python
Responsibilities
Perform advanced AI Static Timing Analysis (STA) for complex chiplet and full chip level; Use AI for timing optimization and data analysis in STA and PnR; Run and build STA tools to analyze and debug timing; Review and debug timing paths, understand constraints, SDC generation, and timing ecosystem generation; Identify convergence risks and work closely with physical design, RTL and DFT teams; Responsible for full timing closer and quality approval from pre-layout STA model through signoff
Seniority
Senior, hands-on IC
