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Chip Design Verification Engineer

Israel, Yokneam💼 Full-time🗓 2026-07-07 → 2026-09-27

Core

Develop shared verification code, methodologies, and infrastructure to ensure design correctness and efficiency for chip design teams.

Role type

Senior IC chip design verification engineer

Builds

Shared verification code, simulation infrastructure, and automation solutions for chip design

Domain

Semiconductor / Chip Design / Verification

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

System Verilog, UVM, Specman, simulation tools, test bench development, coverage evaluation, debugging

Preferred skills

EDA vendor tools, design automation collaboration, training development

Technologies

System Verilog, UVM, Specman, simulation tools

Responsibilities

Develop shared verification code and solutions; create verification methodologies; collaborate with design automation teams; interface with EDA vendors; define verification scope and develop infrastructure; debug simulation failures

Seniority

Mid-level, hands-on IC

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