CAD Layout Design Engineer
Core
Develop digital IP, productivity scripts, and layout guidelines to accelerate SRAM and custom analog layout creation for new technology nodes.
Role type
Senior IC CAD Layout Design Engineer (IP & Methodology)
Builds
Digital IP (PCELLs, SRAM leaf cells), productivity scripts, and layout design guidelines for advanced nodes.
Domain
Semiconductor manufacturing, analog/digital IC design, advanced process nodes (5nm, 3nm, 2nm).
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SRAM/Analog layout design, PCELL development, Cadence SKILL, Python scripting, Perl scripting, Shell scripting, tape-out experience, advanced technology node expertise (5nm/3nm/2nm)
Preferred skills
Machine Learning/Deep Learning/LLM application for layout creation, next-generation tool investigation
Technologies
Cadence SKILL, Python, Perl, Shell, SRAM, PCELL
Responsibilities
Create digital IP to enable layout work in new technology; conduct in-depth studies of new technology to enable design teams; coordinate analysis of new technology and translate into EMIR/DFM/SRAM layout guidelines; investigate next generation tools for layout creation; investigate applications of ML/DL/LLM techniques for layout creation.
Seniority
Senior, hands-on IC
