ASIC Physical Design CAD, Timing Constraint and Analysis
Core
Developing timing analysis and closure methodologies, implementing flow automation, and establishing constraint release processes for large-scale, high-speed semicustom chips.
Role type
Senior IC ASIC Physical Design Engineer (Timing & Constraints)
Builds
Production ASIC chips using deep submicron processes
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA), timing closure, synthesis, constraint definition (SDC), EDA tool evaluation, scripting (Perl/TCL/Python/C++)
Preferred skills
Flow development/automation, RTL simulation and validation
Technologies
Synopsys PrimeTime, Cadence Tempus, Synopsys TCM, Ausdia TimeVision
Responsibilities
Develop timing analysis and closure methodologies; Establish methodologies for timing constraints and SDC release; Take responsibility for EDA tool evaluation and collaboration with vendors
Seniority
Senior, hands-on IC
