DRAM Technology Sr. Layout Design Engineer
Core
Translate schematics into layout for DRAM fabrication reticules and optimize IP layouts for digital and analog circuits.
Role type
Senior IC layout design engineer (DRAM)
Builds
Fabrication reticules and DRAM product layouts
Domain
Semiconductor manufacturing / DRAM technology
Required skills
Custom layout design in advanced CMOS, Physical verification (DRC, LVS, EM), Electromigration/IR drop/Latch-up analysis, Cadence Virtuoso, Mentor Calibre, Area optimization, Power/performance trade-offs
Preferred skills
Layout automation scripting (SKILL), AI-powered tool integration, Global team collaboration, Innovative workflow approaches
Technologies
Cadence Virtuoso, Mentor Calibre, SKILL
Responsibilities
Develop and optimize IP layouts for DRAM products; Perform physical verification activities including DRC, LVS, EM; Collaborate with design and CAD teams to solve layout challenges; Guide team members through layout reviews; Plan and present layout strategies to stakeholders
