ASIC Design Engineer, DMTS/SMTS/MTS
Core
Design and CAD enablement for advanced semiconductor products (NAND, DRAM, HBM, SoC, mixed-signal), leading implementation, signoff, and custom layout activities.
Role type
Senior IC ASIC Design Engineer (Design & Methodology)
Builds
Scalable CAD tools, automation frameworks, design flows, and methodologies for memory and storage products.
Domain
Semiconductor / VLSI / Memory & Storage
Required skills
VLSI and CMOS fundamentals, EDA environments (Cadence, Synopsys, Siemens), Unix/Linux, scripting (Python, Tcl, SKILL, Shell, Perl, C/C++, Java, Lisp), physical design (floor planning, placement, CTS, routing), timing signoff, DFT strategies, parasitic extraction, circuit simulation, DRC/LVS.
Preferred skills
AI-assisted engineering solutions, multi-mode/multi-corner timing analysis, signal integrity analysis, ECO management, silicon bring-up support.
Technologies
Cadence Innovus, Virtuoso, Synopsys ICC2, PrimeTime, Siemens Tessent, Cadence Tempus, Modus
Responsibilities
Develop and maintain infrastructure for circuit build capture, layout, simulation, characterization, implementation, physical verification, and signoff workflows; Lead implementation and signoff activities across physical design, static timing analysis, and design for test; Drive floor planning, power planning, placement, clock tree synthesis, routing, optimization, timing closure, and physical verification; Develop and implement DFT strategies including scan insertion, ATPG, MBIST, LBIST, compression, and verification; Analyze and resolve congestion, IR drop, electromigration, clocking, and signal integrity issues; Partner with architecture, RTL, circuit design, verification, and process technology teams to ensure design readiness and manufacturability.
Seniority
Senior, hands-on IC
