Senior Engineer IP Verification - Digital Design Verification
Core
Define verification scope and strategy for block/chip RTL verification of DRAM architectures, developing testbenches and vectors to demonstrate readiness for tapeout.
Role type
Senior IC digital design verification engineer (DRAM)
Builds
DRAM memory blocks and chips
Domain
Semiconductor / Memory / Digital Design
Required skills
RTL verification, SV-UVM, directed and constrained-random testing, functional coverage analysis, debugging RTL/testbench, scripting (Perl, Python), digital circuit understanding
Preferred skills
AI tool adoption for verification workflows, cross-functional collaboration
Technologies
SV, UVM, Virtuoso, Xcellium, Simvision, Verdi/Verisium
Responsibilities
Define verification scope and strategy; develop and maintain verification testbenches and test vectors; run regressions and analyze failures; close verification metrics; debug RTL and testbench issues; provide verification status to stakeholders
Seniority
Senior, hands-on IC
