Staff Physical Design Engineer, HBM
Core
Backend physical design engineer driving RTL-to-GDSII implementation for high-performance, low-power digital logic in advanced memory products.
Role type
Staff Physical Design Engineer (Digital)
Builds
High-performance memory chips (HBM) and advanced digital logic
Domain
Semiconductor / Memory / Digital Physical Design
Deliverable
production ML models | product features
Required skills
RTL-to-GDSII flow, floorplanning, place & route, clock tree synthesis, timing closure, power integrity analysis, low-power design techniques, scripting (TCL/Python/Perl), cross-functional collaboration
Preferred skills
Advanced technology nodes, high-frequency/high-density designs, memory/HBM experience, 3D-IC and advanced packaging knowledge
Technologies
EDA tools, STA tools, UPF/CPF, DRC/LVS/ANT/DFM flows
Responsibilities
Execute physical design from netlist to GDSII including floorplanning, placement, CTS, routing, and signoff; Drive timing closure across multiple modes and corners; Resolve congestion, IR drop, EM, and power integrity issues; Develop floorplans, power grids, and clocking strategies; Collaborate with RTL designers on partitioning and micro-architecture; Implement low-power techniques like power gating and DVFS; Execute physical verification and support ECOs; Automate flows using scripting; Interface with EDA vendors to debug tools and improve methodologies
Seniority
Staff, hands-on IC with mentorship
