STAFF ENG-HBM-LAYOUT
Core
Design and development of critical mixed-signal, custom digital blocks and full chip level integration for High Bandwidth Memory (HBM) used in AI and high-performance computing.
Role type
Staff IC Layout Design Engineer
Builds
PWF Reticles, advanced packaging solutions, and full chip layouts for HBM
Domain
Semiconductor / VLSI / Memory Technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/custom layout design, Cadence VLE/VXL, Mentor Calibre DRC/LVS, TSV design, DFMEA creation, LVS/DRC/Antenna verification, block-level layout creation (PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier), Reticle development, Full Chip Verification, Layout fundamentals (Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop), Physical verification automation
Preferred skills
AI features for project execution, Multiple Tape out support, Managing multiple layout projects
Technologies
Cadence VLE, Cadence VXL, Mentor Calibre
Responsibilities
Design and co-optimization of mixed-signal and custom digital blocks, Build and tapeout PWF Reticles, Engage with Scribe Design team for Advanced Packaging requirements, TSV design engagement for electrical/thermal/mechanical performance, Creation and Maintenance of DFMEA, Perform layout verification (LVS/DRC/Antenna), Guide junior team-members in Sub block-level layouts, Demonstrate leadership in planning and scheduling
Seniority
Staff, hands-on IC with mentorship