STAFF ENG-HBM-LAYOUT
Core
Design and development of critical mixed-signal, custom digital blocks and full chip level integration for High Bandwidth Memory (HBM) used in AI and high-performance computing.
Role type
Staff IC Layout Design Engineer (HBM/Advanced Packaging)
Builds
PWF Reticles, TSV designs, and full chip layouts for HBM solutions.
Domain
Semiconductor / Memory / Advanced Packaging
Required skills
Analog/custom IC layout design, Mixed-signal block design, Full chip verification (LVS/DRC), Advanced packaging process knowledge, Reticle development, Physical verification automation, Project management, Team leadership
Preferred skills
AI/ML tool usage for layout automation, Multiple tape-out experience
Technologies
Cadence VLE/VXL, Mentor Calibre DRC/LVS
Responsibilities
Design and co-optimize mixed-signal and custom digital blocks, Build and tapeout PWF Reticles, Engage with Scribe and TSV design teams for advanced packaging, Create and maintain DFMEA for packaging processes, Perform layout verification (LVS/DRC/Antenna), Guide junior team members in sub-block layouts, Lead project planning and scheduling
Seniority
Staff, hands-on IC with leadership responsibilities
