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Senior / Principal Layout Engineer – Module Architecture (Pathfinding)

San Jose, CA💼 Full-time💰 $202,000–$202,000🗓 2026-07-27 → 2026-09-26

Core

Lead layout-driven architecture exploration and feasibility studies for next-generation memory modules (DDR6, LPDDR6/7, MRDIMM, SOCAMM2) and interconnects.

Role type

Senior / Principal IC Layout Engineer (Module Architecture & Pathfinding)

Builds

Next-gen memory modules and high-speed interconnects for data centers and computing platforms

Domain

Semiconductor / Memory / High-Speed PCB Design

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

High-speed PCB layout, Signal Integrity (SI), Power Integrity (PI), DDR/LPDDR memory interfaces, Ultra-high-speed parallel interfaces, Transmission line theory, Channel loss mechanisms, PDN design, Decoupling optimization, Routing topology, Pinout tradeoffs, Design rule definition, Cross-functional architecture collaboration, AI tool proficiency

Preferred skills

Advanced HDI technologies, Hybrid bonding, JEDEC standards influence, Mentorship

Technologies

Cadence Allegro, OrCAD

Responsibilities

Lead layout-driven architecture exploration for next-generation memory modules and interconnects; Evaluate form factor, routing topology, and pinout tradeoffs to enable future bandwidth and density targets; Define feasible design envelopes (routing complexity, layer count, escape feasibility, via strategy); Collaborate with SI/PI teams to co-optimize channel topology, loss/reflection/crosstalk mitigation, and return path integrity; Define and influence SI/PI budgets at the module level; Drive adoption of next-generation PCB technologies (ultra-low-loss materials, advanced HDI, hybrid bonding); Help develop next-gen layout methodologies and constraints for >10–20+ Gb/s signaling; Establish design rules bridging architecture, SI/PI, layout, and manufacturing; Drive design reviews, risk assessments, and trade-off analysis; Mentor junior engineers and shape layout best practices.

Seniority

Principal, strategy & mentorship

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