Engineer-std cell layout
Core
Designing and maintaining standard cell layouts for new DRAM products on emerging technologies.
Role type
Senior IC physical design engineer (standard cells)
Builds
PPA-qualified standard cell libraries for DRAM products
Domain
Semiconductor manufacturing / DRAM memory / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Standard cell architecture design, LVS/DRC/Latchup verification, project planning and scheduling, team leadership and mentoring, DTCO collaboration, process-CMOS-CAD negotiation, AI-assisted workflow development
Preferred skills
Experience with new technology nodes, automation of design flows, cross-functional collaboration with international teams
Technologies
DTCO tools, CAD tools, AI-assisted design workflows
Responsibilities
Design and maintain standard cell layouts for new DRAM products; lead layout projects from spec definition to library release; collaborate with DTCO on stdcell architecture; perform layout verification (LVS/DRC/Latchup); guide junior team members in sub-block-level layouts; develop new flows/methodologies to reduce manual effort; negotiate DRC rules with Process, CMOS, and CAD teams.
Seniority
Senior, hands-on IC with leadership responsibilities
