Staff engineer , ASIC AMS Verification
Core
Lead verification for high-speed DDR & ONFI PHY designs at advanced technology nodes, focusing on mixed-signal and analog-mixed-signal (AMS) integration.
Role type
Staff ASIC AMS Verification Engineer
Builds
Scalable, reusable metric-driven verification environments and behavioral models for chip-level verification.
Domain
Semiconductor / Memory Storage / Mixed-Signal Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM environment design, SystemVerilog, Verilog-AMS, logic simulation, RTL debugging, code coverage analysis, analog block understanding (SDLL, DCC, Band gap), DDR/LPDDR JEDEC protocols, NAND ONFI/DFI protocols
Preferred skills
Full-chip co-simulation, power-aware verification (UPF/CPF), mentoring junior engineers
Technologies
SystemVerilog, UVM, Verilog-A, SPICE, GLS, UPF, CPF
Responsibilities
Design scalable verification environments using SystemVerilog/UVM and mixed-signal simulators; Author precise behavioral models to replace heavy SPICE sub-circuits; Support top-level gate-level simulations and mixed-signal co-simulations; Own IP and sub-system verification from test plan to signoff; Mentor and coach junior team members; Collaborate with digital and analog designers
Seniority
Staff, hands-on IC with mentorship