Package Health Yield (Senior/Staff/Principal) Engineer, APTD
Core
Develop advanced packaging technology strategies for high-performance memory products, focusing on test architecture, coverage, and yield optimization to ensure robust packaging solutions.
Role type
Senior/Staff/Principal IC semiconductor packaging test engineer
Builds
High-bandwidth memory (HBM) packages and advanced packaging solutions for AI and supercomputing applications
Domain
Semiconductor manufacturing, advanced packaging, high-performance memory
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Test architecture definition, wafer and die-level test coverage optimization, electrical characterization, failure analysis, DFT co-development, probe yield management, simulation tools, data analysis, scripting (Python, MATLAB, JMP)
Preferred skills
Experience with complex semiconductor products, cross-functional collaboration, customer test flow readiness
Technologies
Python, MATLAB, JMP, simulation tools, test equipment
Responsibilities
Define and validate test coverage for wafer and die processes; perform electrical characterization and failure analysis of advanced packages; co-develop new DFTs with cross-functional teams; enhance test fail debugging to meet probe yield targets; contribute to product roadmap from test architecture perspective; co-work with PI for Test Vehicle validations; drive customer test flow readiness activities
Seniority
Senior/Staff/Principal, hands-on IC