Package Health Yield (Senior/Staff/Principal) Engineer, APTD
Core
Develop advanced packaging technology strategies for high-performance memory products (HBM), focusing on test architecture, coverage, yield, and reliability characterization.
Role type
Senior IC semiconductor package test engineer
Builds
High bandwidth memory (HBM) packages and test vehicles for AI and supercomputing applications
Domain
Semiconductor manufacturing / Advanced Packaging / High Performance Memory
Required skills
Test architecture definition, Wafer and die-level test coverage optimization, Electrical characterization, Failure analysis, DFT development, Yield management, Simulation tools, Data analysis and scripting (Python, MATLAB, JMP)
Preferred skills
Experience with complex semiconductor products, Cross-functional collaboration, Customer test flow readiness
Technologies
HBM, DFT, Simulation tools, Test equipment, Python, MATLAB, JMP
Responsibilities
Define and validate test coverage for wafer and die processes; Perform electrical characterization and failure analysis of advanced packages; Co-develop new DFTs with cross-functional teams; Enhance test fail debugging to meet probe yield targets; Contribute to product roadmap from test architecture perspective; Support Test Vehicle (TV) validations and customer test flow readiness.
Seniority
Senior, hands-on IC