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Principal Design Engineer, DRAM

Boise, ID - Main Site💼 Full-time🗓 2026-07-17 → 2026-07-31

Core

Designing testability, circuit architecture, and methodology for advanced memory products to ensure they are robust and production-ready.

Role type

Principal Design Engineer (Design for Test)

Builds

Advanced memory products (DRAM) with integrated testability and verification solutions.

Domain

Semiconductor / Memory / Digital & Mixed-Signal Circuit Design

Deliverable

production ML models | product features | infrastructure

Required skills

Digital or mixed-signal circuit design, Design-for-Test (DFT) concepts, testmode development, scan-based methodologies, cross-functional collaboration, modeling and simulation

Preferred skills

DFT circuit design for complex SoC or memory products, DFT verification flows, EDA tools, AI-assisted design techniques

Technologies

EDA tools, simulation environments

Responsibilities

Define and implement DFT and testmode requirements; Design and evaluate new DFT circuit and architectural solutions; Influence early design planning by shaping DFT architecture and strategies; Validate DFT solutions through modeling, simulation, and review; Collaborate across design, verification, product engineering, and manufacturing to meet coverage and quality goals

Seniority

Principal, hands-on IC with architectural influence

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