SR Engineer, ASIC DFT
Core
Implementing Design for Test (DFT) methodologies for Micron IPs and Memory controllers (SOCs) to ensure high-quality storage products with low defect rates.
Role type
Senior IC ASIC DFT Engineer
Builds
High-performance DRAM, NAND, and NOR memory and storage products
Domain
Semiconductor / Memory and Storage
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Scan Codec insertion, Memory BIST and Repair implementation, Logic BIST, ATPG, BSCAN & JTAG, Fault Simulation, ATPG Fault models, SDF annotated gate level verification, Scan and Memory Diagnosis, Verilog, VHDL, C/C++, TCL, Perl, Python, Siemens tools, Synopsys tools, Cadence tools
Preferred skills
IEEE 1149.6, 1500 and 1838 knowledge, Hierarchical Scan implementations, Multi-clock domains handling, Low power design implementation, SSN, 2.5D or 3D IC DFT implementation
Technologies
Verilog, VHDL, C/C++, TCL, Perl, Python, Siemens, Synopsys, Cadence
Responsibilities
Accountable for innovative DFT implementation (Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level, Generate and validate ATPG patterns using simulations, Validate the DFT implementation using RTL and Gate level simulation, Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation, Support the Silicon bring up activities, Chip in to the overall DFT methodology development
Seniority
Senior, hands-on IC
