STAFF ASIC Design Engineer
Core
Design and implement complex logic for next-generation solid-state drive controllers, covering RTL development, integration, and validation from concept to production silicon.
Role type
Staff ASIC Design Engineer
Builds
Solid-state drive controllers and associated IP blocks
Domain
Semiconductor / Storage / Memory
Required skills
RTL design (Verilog/SystemVerilog), Digital ASIC Design methodology, Large-scale design projects, ASIC design flow tools (Synthesis, Lint, CDC, ECO, timing analysis), Design/Verification CAD tools (ncsim, Design Compiler, Formality, PrimeTime), AMBA AXI/AHB protocols, High-speed protocols (PCIe, USB, SATA, DisplayPort, HDMI), Storage/Memory protocols (NVMe, SCSI, CXL, DDR)
Preferred skills
Python/TCL/PERL scripting, AI-assisted engineering tools, AI/ML concepts, EDA tool automation
Technologies
Verilog, SystemVerilog, Python, TCL, PERL, ncsim, Design Compiler, Formality, PrimeTime, PCIe, USB, SATA, NVMe, CXL, DDR
Responsibilities
Design, implement, and debug complex logic designs; Integrate IP into larger complex IPs; Support front-end integration (Lint, CDC, Synthesis, ECO); Implement design automation using Python or other languages; Collaborate with SOC Design, Verification, Emulation, STA, and Physical Design teams; Use AI-assisted tools to enhance code quality and accelerate debugging.
Seniority
Staff, hands-on IC
