Senior Analog and Mixed Signal Design Engineer
Core
Senior IC design expert owning SerDes link architecture and transistor-level design of critical analog front-end and clocking blocks for Intel's leading-edge process technologies.
Role type
Senior individual-contributor analog/mixed-signal design engineer (SerDes)
Builds
High-speed SerDes reference designs, test chips, and silicon for next-generation wireline standards (PCIe, UCIe, HBM, PAM4)
Domain
Semiconductor / High-speed I/O / Analog Mixed-Signal
Required skills
SerDes link architecture, transistor-level circuit design, link budget analysis, equalization strategy, MATLAB/Python modeling, silicon bring-up, design-technology co-optimization
Preferred skills
FinFET/GAA CMOS design, 56 Gb/s+ PAM4 experience, time-interleaved ADC design, package/channel co-design, ISSCC/VLSI publications
Technologies
MATLAB, Python, COM, IBIS-AMI, SST, CML, CTLE, DFE, ADC, PLL, PCIe, UCIe, HBM
Responsibilities
Define SerDes link architecture for 224G/448G-class interfaces; Build system-level link models; Lead transistor-level design of TX drivers, RX AFE, and clocking circuits; Drive test-chip definition and silicon bring-up; Translate requirements into process/PDK specifications; Provide technical leadership and mentorship
Seniority
Senior, hands-on IC
