Pre-Silicon Verification Engineer
Core
Develop verification environments, tests, and debug pre-silicon issues for clock generator IPs (PLL/FLL) to ensure functional accuracy and reliability.
Role type
Senior IC design verification engineer (clock generator IP)
Builds
Clock generator IPs (PLL/FLL) for Intel's product development lifecycle
Domain
Semiconductor / Digital & Mixed-Signal IC Design
Required skills
System Verilog, UVM, Python, Perl, EDA tools, Mixed Signal Validation, AMS simulations, Schematic debugging, Test bench development, Root-cause analysis, Technical documentation
Preferred skills
PLL/FLL or SOC clocking expertise, RTL development experience
Technologies
System Verilog, UVM, Python, Perl, EDA tools
Responsibilities
Develop test benches and verification environments; Perform functional verification for clock generator IPs; Maintain verification infrastructure; Debug and root-cause pre-silicon issues; Document test plans; Collaborate with architects, RTL developers, and analog design teams; Lead Mixed Signal Validation activities.
Seniority
Senior, hands-on IC
