Senior Verification Engineer
Core
Senior IP Design Verification Engineer leading verification planning, environment creation, and bug resolution for complex NIC, IPU, and AI chip designs.
Role type
Senior IC verification engineer (hardware)
Builds
Scalable verification environments, test benches, VIPs, and behavioral models for ASIC/SOC IPs
Domain
Semiconductor hardware design (NIC, IPU, AI)
Deliverable
production ML models
Required skills
System Verilog, OVM/UVM, formal verification, digital design fundamentals, microarchitecture, simulation, debugging tools
Preferred skills
Formal property verification, System Verilog Assertions, code/functional coverage, AMBA protocols (APB, AXI), switching/routing protocols (Ethernet, IPSec, DTLS, MACSec), scripting (Python, Perl, Shell), AI-assisted verification flows
Technologies
System Verilog, OVM, UVM, Python, Perl, Shell, SystemC, Ethernet, IPSec, DTLS, MACSec, AMBA, AXI, APB
Responsibilities
Own verification planning and execution for key IP features; Build scalable verification environments and targeted test plans; Collaborate with architecture, design, and software teams; Drive ownership of critical blocks and verification components; Lead IP delivery to multiple customers; Drive convergence of simulation and formal verification; Mentor and develop verification engineers
Seniority
Senior, hands-on IC with mentorship
