E-Core CPU Design Automation Engineer
Core
Develop, debug, and support backend physical design tools, flows, and methodologies for high-performance E-core CPUs (laptops, desktops, 5G base stations, AI devices).
Role type
Senior IC physical design automation engineer
Builds
High-performance, low-power CPU blocks and full chips
Domain
Semiconductor / Microprocessor / VLSI
Required skills
RTL2GDS standard cell design, static timing analysis (STA), formal equivalence verification, power consumption analysis, electrical rule checking (ERC), circuit reliability analysis, Python scripting, Perl scripting, Tcl scripting, VLSI design automation algorithms, EDA tool flows (Synopsys, Cadence, Mentor Graphics), timing closure methodology, worst-case corner analysis, spice circuit simulation, noise analysis, cross talk analysis, OCV effects, budget constraints
Preferred skills
Transistor-level design, microprocessor backend design, AI capabilities for operational efficiency
Technologies
Python, Perl, Tcl, Synopsys, Cadence, Mentor Graphics
Responsibilities
Develop and debug tools and flows for backend physical design; Perform analysis of synthesis, place-and-route, floor planning, and signoff; Work with design teams to debug tool issues; Collaborate with EDA vendors to enhance tool capabilities; Create documentation and guidelines; Leverage AI to enhance efficiency
Seniority
Experienced Hire, hands-on IC
