Senior Signal Integrity Engineer (Hands-on)
Core
Lead hardware design and signal integrity activities for high-speed interfaces (PCIe, Ethernet, DDR) in semiconductor ASIC development, focusing on EM simulation, model correlation, and design sign-off.
Role type
Senior hands-on IC signal integrity engineer
Builds
High-speed I/O interfaces for Ethernet Infrastructure Processing Unit (IPU) and Foundation NIC (FNIC) product lines
Domain
Semiconductor ASIC design, high-speed digital interfaces, electromagnetic simulation
Required skills
Signal Integrity engineering, EM simulation (HFSS, CST, ADS, Simbeor), PCB layout and stack-up design, RF circuits and wave propagation, high-speed interface modeling (PCIe, Ethernet, DDR), EDA tools, CAD tools (Allegro, Expedition), lab measurement (Oscilloscopes, VNA, TDR, BERT), AI-based automation techniques, debugging and root cause analysis
Preferred skills
Experience with manufacturing variation impact modeling, cross-functional team leadership, technical reviews
Technologies
HFSS, CST, ADS, Simbeor, Cadence Allegro, Mentor Expedition, high-end Oscilloscopes, VNA, TDR, BERT
Responsibilities
Model channel elements in 3D/2D EM simulation tools for pre- and post-layout stages, lead signal integrity activities for multiple high-speed/low-speed interfaces, correlate models with post-manufacturing measurements, run sign-off simulation flows, provide feedback to design teams, perform lab experiments for signal measurement, identify and qualify AI-based automation solutions
Seniority
Senior, hands-on IC
