Qubit Control Physical Design Engineer
Core
Deliver high-performance physical designs for advanced semiconductor technologies, optimizing power, performance, and area (PPA) from synthesis to sign-off.
Role type
Senior IC physical design engineer (semiconductor)
Builds
High-performance silicon chips and chiplet-based architectures
Domain
Semiconductor manufacturing / Chip design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (Note: Corrected to 'product features' or 'infrastructure' based on standard mapping, but strictly following the prompt's allowed list, 'product features' fits best for a chip design role delivering a product, or 'infrastructure' for the silicon itself. Let's use 'product features' as the chip is the product feature for the system, or better yet, since the prompt list is fixed, I must choose one. The role builds the physical chip. 'product features' is the closest fit for a deliverable that goes into a market product. However, 'infrastructure' is also valid for silicon. Let's select 'product features' as the chip enables the product.)
Required skills
RTL-to-GDS design convergence, floor planning, timing constraints definition, synthesis, place-and-route, Python scripting, Perl scripting, TCL scripting, functional equivalence verification (FEV), engineering change orders (ECOs), chiplet integration, advanced packaging techniques, AI tool utilization
Preferred skills
Static timing analysis (SerDes, UCIe), EDA tool development (Java, C++), asynchronous architectures, power-efficient design techniques, high-frequency physical design
Technologies
Cadence Virtuoso, Synopsys Fusion Compiler, Python, Perl, TCL, Java, C++