Sr Deep Learning Verification Engineer
Core
Validate and optimize next-generation NPU silicon solutions and AI hardware components through pre-silicon functional verification.
Role type
Senior IC hardware verification engineer (NPU/ASIC)
Builds
Next-generation NPU IP portfolio and AI accelerator designs
Domain
Semiconductor hardware + AI accelerators
Deliverable
production ML models | product features
Required skills
System Verilog, UVM, OVM, random test generation, bus functional models (BFMs), formal verification, coverage closure, SVA properties
Preferred skills
C-based software driver development, low power/high performance design validation, SoC/NoC/AMBA protocols, Git/CI practices, deep learning frameworks (TensorFlow/PyTorch)
Technologies
VCS, System Verilog, UVM, OVM, Git, CI tools
Responsibilities
Architect and implement verification environments from planning to signoff; develop test plans, cases, and random test generators; implement checkers, scoreboards, and covergroups; create software-based testcases for functional and performance testing; collaborate with cross-functional teams to address AI requirements and influence product roadmap.
Seniority
Senior, hands-on IC
